The present invention relates to afield-effect transistor, a bipolar transistor, and methods of fabricating the same.
A typical mobile telephone has a transmit/receive switching device for switching a single antenna between transmission and reception. As the transmit/receive switching device, an RF switching device composed of a field-effect transistor (FET) using GaAs has been used, of which a reduction in loss has been demanded strongly.
To achieve a loss reduction in the RF switching device, it is necessary to reduce the source-to-drain resistance of the switching device in the on state and reduce the source-to-drain capacitance of the switching device in the off state.
Compared with the PDC (personal digital cellular) method standardized in Japan, the GSM (global system for mobile communication) method, which is a communication method standardized in European countries, features a large antenna output. To provide a large power handling capability even at a low control voltage, therefore, a multigate FET device in which one FET device has a plurality of gate electrodes should be used. However, since a conventional multigate FET device has a high on-state resistance, the insertion of the FET device causes a large insertion loss.
As an approach to the solution of the problem, the use of a FET device having a multigate electrode formed by self alignment as the RF switching device may be considered. By using the RF switching device having the self-aligned multigate electrode, the distance between the source and drain electrodes is reduced so that the source-to-drain resistance of the device in the on state is reduced. In addition, since the self-aligned gate of the FET device is formed by self alignment relative to the source and drain electrodes thereof, a mask placement error does not occur during the formation of the gate electrode by photolithography.
Of heterojunction bipolar transistors (HBTs) which are active devices different from FETs, the one having the base electrode formed by self alignment relative to the emitter electrode is effective in reducing the base resistance. In the case of the HBT device also, a mask placement error does not occur during the formation of the base electrode by photolithography, similarly to the aforesaid FET device having the gate electrode formed by self alignment.
A conventional FET device having a self-aligned gate electrode will be described with reference to the drawings.
FIG. 11 shows a cross-sectional structure in the direction of the gate length of the conventional FET device disclosed in Japanese Unexamined Patent Publication No. HEI 8-115924.
As shown in FIG. 11, a conductive layer (channel layer) 102 composed of n-type GaAs doped with silicon (Si) as an impurity and a Schottky layer 103 composed of undoped aluminum gallium arsenide (AlGaAs) are formed successively on a semi-insulating substrate 101 made of gallium arsenide (GaAs). An isolation region 104 as an insulated region is formed in the formed conductive layer 102 and Schottky layer 103 to reach the semi-insulating substrate 101 and electrically insulated from other devices (not shown).
A pair of contact layers 105 each composed of n+-type indium gallium arsenide heavily doped with Si are formed on a region of the Schottky layer 103 on which the device is to be formed. Ohmic electrodes 106 each composed of a refractory metal such as tungsten silicide (WSi) and serving as a source or drain electrode are formed on the pair of contact layers 105, respectively.
On a region of the Schottky layer 103 lying between the contact layers 105, a gate electrode 107A is formed at a distance from the side surfaces of the contact layers 105. Metal layers 107B composed of the same material as composing the gate electrode 107A are formed on the respective ohmic electrodes 106. The entire surface of the FET device including the gate electrode 107A and the metal layers 107B is covered with a protective insulating film 108 composed of a silicon oxide or the like. On the portions of the protective insulating film 108 located above the respective metal layers 107B, there are disposed Au wiring layers 109 for electrical connection with the respective metal layers 107B.
A method of fabricating the FET device thus structured will be described herein below.
First, the conductive layer 102, the Schottky layer 103, and the contact layer 105 are epitaxially grown in succession on the semi-insulating substrate 101. Subsequently, a metal film composed of WSi for forming the ohmic electrodes is formed by sputtering over the entire surface of the contact layer 105.
Next, the metal film is patterned by reactive anisotropic dry etching by using, as a mask, a resist pattern formed by photolithography to have the ohmic electrode pattern, whereby the ohmic electrodes 106 composed of Wsi are formed.
Next, isotropic wet etching is performed with respect to the contact layer 105 by using a solution mixture of, e.g., phosphoric acid, aqueous hydrogen peroxide, and water, thereby removing the portion of the contact layer 105 corresponding to the gate electrode. Then, a specified amount of side etching is performed with respect to the portions of the contact layers 105 located under the ohmic electrodes 106, thereby forming each of the contact layers 105 into an undercut configuration relative to the ohmic electrodes 106.
Next, the isolation region 104 is formed in the peripheral portion of the FET device by ion implantation. Thereafter, a metal film for forming the gate electrode is vapor deposited to a thickness smaller than the film thickness of the contact layer 105 over the entire surface of the semi-insulating substrate 101, thereby forming the gate electrode 107A by self alignment relative to the ohmic electrodes 106.
Next, the protective insulating film 108 composed of the silicon oxide is formed over the entire surface of the semi-insulating substrate 101. After that, the Au wiring layers 109 are formed by plating in the contact portions of the protective insulating film 108 for contact with the ohmic electrodes 106.
If the FET device having the self-aligned gate electrode is to be used as the switching device, it is required to reduce the source-to-drain resistance of the switching device in the on state and reduce the source-to-drain capacitance of the switching device in the off state, as stated previously.
In reducing the off-state source-to-drain parasitic capacitance of the FET device having the gate electrode 107A formed by self alignment shown in FIG. 11, it is effective to reduce the area of each of the source and drain electrodes (ohmic electrodes 106) to the order of micrometers. By miniaturizing the source and drain electrodes, the chip size can be reduced drastically.
However, the conventional method of fabricating the field-effect transistor has the problem of an increase in contact resistance due to a reduction in contact area between each of the ohmic electrode 106 and the contact layer 105, which is caused by side etching (undercut) proceeding at the portions of the contact layers 105 underlying the ohmic electrodes 106 in the wet etching process performed with respect to the contact layers 105. If the ohmic electrode 106 with a width of 2.0 xcexcm is etched by wet etching to a depth of 0. 5 xcexcm, e.g., the width of the portion of the contact layer 105 underlying the ohmic electrode 106 becomes 1 xcexcm and the contact resistance is approximately doubled. This presents a new problem encountered by the ongoing miniaturization of the FET device having the self-aligned gate electrode.
To reduce the contact resistance, non-alloy electrodes which do not form alloy layers at the interfaces with the contact layers 105 and therefore do not require a heat treatment may be used as the ohmic electrodes 106. In the case of using a multilayer structure of, e.g., titanium (Ti), platinum (Pt), and gold (Au), which are named in order of increasing distance from the contact layer 105, the contact resistance of the non-alloy electrode is reduced by about an order of magnitude compared with the case of using WSi.
If the multilayer structure is etched by using a solution mixture of phosphoric acid, aqueous hydrogen peroxide, and water, the etching solution penetrates the interface between each of the contact layers 105 and the ohmic electrode 106 composed of the non-alloy electrode to etch the interface into a wedge-shaped configuration, so that the contact area between the contact layer 105 and the ohmic electrode 106 is reduced to disadvantageously increase the contact resistance. In the worst case, the ohmic electrode 106 peels off the contact layer 105.
Thus, the gate electrode 107A of the conventional FET device is formed by self alignment by utilizing the configuration of the contact layer 105 which is undercut relative to the ohmic electrode 106, i.e., by utilizing the configuration of the ohmic electrode 106 which is overhanging from the contact layer 105. As a consequence, the area of the contact layer 105 is inevitably smaller than the area of the ohmic electrode 106.
Similar problems are also encountered by the emitter electrode of the HBT device.
The present invention has been achieved to solve the foregoing conventional problems and it is therefore an object of the present invention to prevent, in a FET device having a self-aligned gate electrode or a HBT device having a self-aligned base electrode, an increase in contact resistance due to a reduction in the contact area between the electrode and a semiconductor layer.
To attain the object, the present invention provides a field-effect transistor wherein semiconductor layers each occupying an area nearly equal to the area occupied by the ohmic electrode are disposed between the contact layers and the ohmic electrodes each having an overhanging configuration protruding from the contact layer.
To attain the object, the present invention provides a bipolar transistor wherein a semiconductor layer occupying an area nearly equal to the area occupied by the emitter electrode is disposed between an emitter layer and the emitter electrode having an overhanging configuration protruding from the emitter layer.
Specifically, the field-effect transistor according to the present invention comprises: a substrate having a channel layer; first semiconductor layers disposed in at least two regions located above the channel layer and spaced apart in a direction parallel to a substrate surface; second semiconductor layers disposed on the respective first semiconductor layers to protrude from respective side surfaces of the first semiconductor layers; ohmic electrodes disposed on the respective second semiconductor layers; and a gate electrode disposed in a region located above the channel region and lying between the first semiconductor layers in spaced relation to the side surfaces of the first semiconductor layers.
Since the field-effect transistor according to the present invention has the second semiconductor layers disposed between the first semiconductor layers as the contact layers and the ohmic electrodes overlying the first semiconductor layers to protrude from the side surfaces of the first semiconductor layers, the second semiconductor layers and the ohmic electrodes have equal contact areas, so that the contact resistance between each of the ohmic electrodes and the second semiconductor layer is not increased even if the first semiconductor layers are reduced in size.
In the field-effect transistor of the present invention, each of the first semiconductor layers is preferably composed of gallium arsenide and each of the second semiconductor layers is preferably composed of indium gallium arsenide.
In the field-effect transistor of the present invention, each of the ohmic electrodes is preferably composed of a multilayer structure including a plurality of metal layers, of which the metal layer closer to the substrate preferably contains titanium.
A first method of fabricating the field-effect transistor according to the present invention comprises: successively forming a first semiconductor layer and a second semiconductor layer above a substrate having a channel layer; forming, on the second semiconductor layer, a mask pattern in an island configuration composed of at least two islands disposed at a distance; performing etching with respect to the second semiconductor layer masked with the mask pattern to pattern the second semiconductor layer into the island configuration; performing etching with respect to the first semiconductor layer masked with the second semiconductor layers in the island configuration such that the first semiconductor layer has the island configuration which is undercut relative to the second semiconductor layers; and, after removing the mask pattern, depositing a metal layer over an entire surface of the substrate including the second semiconductor layers in the island configuration to form a gate electrode by self alignment in a region located above the substrate and lying between the first semiconductor layers in the island configuration and form ohmic electrodes each composed of the metal layer.
Since the first method of fabricating the field-effect transistor performs etching with respect to the first semiconductor layer masked with the second semiconductor layers in the island configuration such that the first semiconductor layer has the undercut configuration relative to the second semiconductor layers, the second semiconductor layers and the metal layers formed on the second semiconductor layers by using the same mask pattern as used to pattern the second semiconductor layers protrude from the side surfaces of the first semiconductor layers. Accordingly, the second semiconductor layers and the metal layers serving as the ohmic electrodes have equal contact areas. Even if the first semiconductor layers are reduced in size, therefore, the contact resistance between each of the metal layers and the second semiconductor layer is not increased.
A second method of fabricating the field-effect transistor according to the present invention comprises: successively forming a first semiconductor layer, a second semiconductor layer, and a first metal layer above a substrate having a channel layer; forming, on the first metal layer, a mask pattern in an island configuration composed of at least two islands disposed at a distance; performing etching with respect to the first metal layer and second semiconductor layer masked with the mask pattern to pattern each of the first metal layer and second semiconductor layer into the island configuration; performing etching with respect to the first semiconductor layer masked with the second semiconductor layers in the island configuration such that the first semiconductor layer has the island configuration which is undercut relative to the second semiconductor layers; and, after removing the mask pattern, depositing a second metal layer over an entire surface of the substrate including the first metal layers in the island configuration to form a gate electrode by self alignment in a region located above the substrate and lying between the first semiconductor layers in the island configuration and form ohmic electrodes each composed of the first and second metal layers.
Besides achieving the same effects as achieved by the first method of fabricating the field-effect transistor, the second method of fabricating the field-effect transistor forms the ohmic electrodes from the first and second metal layers so that the film thickness of each of the ohmic electrodes is no more restricted by the film thickness of the second semiconductor layer forming the gate electrode. This increases process flexibility and reduces the resistance of each of the ohmic electrodes.
In the first or second method of fabricating the field-effect transistor, each of the first semiconductor layers is preferably composed of gallium arsenide and each of the second semiconductor layers is preferably composed of indium gallium arsenide.
In the first or second method of fabricating the field-effect transistor, each of the ohmic electrodes is preferably composed of a multilayer structure including a plurality of metal layers, of which the metal layer closer to the substrate preferably contains titanium.
In the first or second method of fabricating the field-effect transistor, the etching step performed with respect to the first semiconductor layer preferably includes the step of: performing wet etching using a solution mixture containing sodium citrate, aqueous hydrogen peroxide, and water.
In the first or second method of fabricating the field-effect transistor, the etching step performed with respect to the first semiconductor layer preferably includes the steps of: etching the first semiconductor layer in a direction perpendicular to the substrate surface by anisotropic selective dry etching; and etching the first semiconductor layer in a direction parallel to the substrate surface by isotropic selective dry etching.
The bipolar transistor according to the present invention comprises: a collector layer disposed above a substrate; a base layer disposed on the collector layer; a first semiconductor layer disposed above the base layer and a base electrode disposed in spaced relation to the first semiconductor layer; a second semiconductor layer disposed on the first semiconductor layer to protrude from side surfaces of the first semiconductor layer; and an emitter electrode disposed on the second semiconductor layer.
Since the bipolar transistor according to the present invention has the second semiconductor layer disposed between the first semiconductor layer disposed in overlying and spaced relation to the base layer and the emitter electrode overlying the first semiconductor layer to protrude from the side surfaces of the first semiconductor layer, the second semiconductor layer and the emitter electrode have equal contact areas. Even if the first semiconductor layer is reduced in size, therefore, the contact resistance between the emitter electrode and the second semiconductor layer is not increased.
In the bipolar transistor of the present invention, the first semiconductor layer is preferably composed of gallium arsenide and the second semiconductor layer is preferably composed of indium gallium arsenide.
In the bipolar transistor of the present invention, the emitter electrode is preferably composed of a multilayer structure including a plurality of metal layers, of which the metal layer closer to the substrate preferably contains titanium.
A first method of fabricating the bipolar transistor according to the present invention comprises: successively forming a base layer, a first semiconductor layer, and a second semiconductor layer above a substrate; forming a mask pattern in an island configuration on the second semiconductor layer and performing etching with respect to the second semiconductor layer masked with the formed mask pattern to pattern the second semiconductor layer into the island configuration; performing etching with respect to the first semiconductor layer masked with the second semiconductor layer in the island configuration such that the first semiconductor layer has the island configuration which is undercut relative to the second semiconductor layer; and after removing the mask pattern, depositing a metal layer over an entire surface of the base layer including the second semiconductor layer in the island configuration to form, on the base layer, a base electrode by self alignment in spaced and adjacent relation to the first semiconductor layer in the island configuration and form an emitter electrode composed of the metal layer.
Since the first method of fabricating the bipolar transistor performs etching with respect to the first semiconductor layer masked with the second semiconductor layer in the island configuration such that the first semiconductor layer has the undercut configuration relative to the second semiconductor layer, the second semiconductor layer is formed to protrude from the side surfaces of the first semiconductor layer. Accordingly, the second semiconductor layer and the metal layer serving as the emitter electrode have equal contact areas. Even if the first semiconductor layer is reduced in size, therefore, the contact resistance between the metal layer and the second semiconductor layer is not increased.
A second method of fabricating the bipolar transistor according to the present invention comprises: successively forming a base layer, a first semiconductor layer, a second semiconductor layer, and a first metal layer above a substrate; forming a mask pattern in an island configuration on the first metal layer and performing etching with respect to the first metal layer and second semiconductor layer masked with the formed mask pattern to pattern each of the first metal layer and second semiconductor layer into the island configuration; performing etching with respect to the first semiconductor layer masked with the second semiconductor layer in the island configuration such that the first semiconductor layer has the island configuration which is undercut relative to the second semiconductor layer; and after removing the mask pattern, depositing a second metal layer over an entire surface of the base layer including the first metal layer in the island configuration to form, on the base layer, a base electrode by self alignment in spaced and adjacent relation to the first semiconductor layer in the island configuration and form an emitter electrode composed of the second metal layer.
Besides achieving the same effects as achieved by the first method of fabricating the bipolar transistor, the second method of fabricating the bipolar transistor forms the emitter electrode from the first and second metal layers so that the film thickness of the emitter electrode is no more restricted by the film thickness of the second metal layer forming the base electrode. This increases process flexibility and reduces the resistance of the emitter electrode.
In the first or second method of fabricating the bipolar transistor, the first semiconductor layer is preferably composed of gallium arsenide and the second semiconductor layer is preferably composed of indium gallium arsenide.
In the first or second method of fabricating the bipolar transistor, the emitter electrode is preferably composed of a multilayer structure including a plurality of metal layers, of which the metal layer closer to the substrate preferably contains titanium.
In the first or second method of fabricating the bipolar transistor, the etching step performed with respect to the first semiconductor layer preferably includes the step of: performing wet etching using a solution mixture containing sodium citrate, aqueous hydrogen peroxide, and water.
In the first or second method of fabricating the bipolar transistor, the etching step performed with respect to the first semiconductor layer preferably includes the steps of: etching the first semiconductor layer in a direction perpendicular to the substrate surface by anisotropic selective dry etching; and etching the first semiconductor layer in a direction parallel to the substrate surface by isotropic selective dry etching.